Basic Compiler v2.0
IntroductionThe Xilinx® LogiCORE™ IP DUC/DDC Compilerimplements high-performance, optimized Digital UpandDown-Converter modules for use in wireless basestations and other suitable appliions. In addition to awide range of parameter options, resource trade-offoptions are available to tailor the core to a particularappliion.
Ftures• erates Digital Up-Converter modules for arange of output sample rates between 30.76 and
245.76 MHz• erates Digital Down-Converter modules for arange of input sample rates between 30.76 and
184.32 MHz• Supports LTE (1.4, 3, 5, 10, 15 and 20 MHzchannels), TD-SMA (1.6 MHz channel) and WMA
(5 MHz channel)
• Supports up to 30 carriers (maximum dependentupon wireless standard and channel bandwidth)
• Implementation options to configure clock rate,enable optional control signals, and set resource usage preferences
• Supports Fs/4 IF down-mixing in DDCconfiguration
• Supports programmable carrier frequencies(within the limits imposed by wireless standard)
• Supports fixed carrier phase offsets between 0 and2
• Supports selectable carrier relative gain levels• Data interfaces compliant with AXI4-Strmstandard, allowing simple integration into signalprocessing data flows• sy-to-use programming interface compliantwith AMBA® 3 APB specifiion• Graphical User Interface (GUI) ftures: resourcnd latency estimation, frequency and phase rasterreporting• For use with Xilinx CORE ™ tool v14.3and Vivado™ Design Suite 2012.3.
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